1. Field of the Invention
This invention relates to multi-level non-volatile semiconductor memory and to access methods that reduce fluctuations in a row line voltage during reading from or writing to a multi-level or multi-bit memory cell.
2. Description of Related Art
Multi-level semiconductor memory devices store an analog value or multiple bits of information in each memory cell. Conventionally, the threshold voltage of a floating gate transistor in a memory cell indicates the value or information stored in the memory cell. Accordingly, storing and retrieving several bits of information or an analog value with accuracy require precise methods for writing and reading the threshold voltage of the floating gate transistor.
One read operation for a multi-level memory varies the voltage on a row line that is attached to the control gate of a selected memory cell and senses the transition between a conductive and a non-conductive state of the selected memory cell. The transition occurs at a row line voltage that is about equal to the threshold voltage of the memory cell. U.S. Pat. Nos. 5,694,356; 5,748,534; and 5,748,533 describe some methods for reading a threshold voltage based on a memory cell's response to a varying row line voltage. For an analog memory, the transition voltage can be sampled and output as the result of the read operation. For a multi-bit-per-cell memory, that analog voltage can be converted to a digital value or alternatively a digital counter, which is synchronized with the changes in the row line voltage, can be stopped to provide a direct digital readout when a memory cell transits between the conductive and non-conductive states. U.S. patent application Ser. No. 09/053,716 describes multi-bit-per-cell memories using counters in the read circuits.
Variation of the row line voltage is also common during write operations. For example, one known write operation applies a high voltage to a row line during each of a series of program cycles. The high voltage on the row line combined with appropriate voltages on the source and drain of a selected memory cell changes the threshold voltage of the selected memory cell by a mechanism such as channel hot electron injection or Fowler-Nordheim tunneling. During a series of verify cycles, which are between program cycles, a write circuit drops the row line voltage to a level corresponding to the target threshold voltage of the write operation and then senses the conductivity of the selected memory cell. When one of the verify cycles senses a change in the conductivity of the selected memory cell, the threshold voltage has reached the target level, and the write operation is complete.
The read and write methods that vary the row line voltage have some disadvantages. In particular, the row lines for large memory arrays can have a relatively high capacitance. Accordingly, changing the row line voltage requires a relatively high current and a relatively large driver circuit. The row line voltages are typically high and require large charge pump circuits. Even with large drivers and charge pump circuits, the charging and discharging of a row line are subject to RC time delays. Further, the changes in the current create noise that can disturb the accuracy of the memory access. Additionally, read and write methods that vary the word line voltage according to a value being written or according to a result that a read operation generates are difficult to use for simultaneous accesses of two or more memory cells on the same row line. In particular, the change in the row line voltage for one memory cell being accessed may be inappropriate for access of another memory cell in the same row. Accordingly, implementing parallel read operations in a multi-level or multi-bit-per-cell array can be complicated.
A known read method that avoids changing the row line voltage applies a fixed voltage to the row line coupled to the selected cell and to a set of reference cells in the same row. The reference cells have different threshold voltages corresponding to the different values that can be stored in a memory cell. Each of the selected memory cell and the reference cells conducts a current that depends on the threshold voltage of the cell. A read circuit identifies the reference cell that has a current approximately equal to the current through the selected memory cell, and the value associated with the identified reference cell is the value read from the selected cell. This approach requires a number of reference cells that increases exponentially with the number of bits stored in each memory cell and linearly with the number of rows.
U.S. patent application Ser. No. 09/224,656 describes a write method that applies a programming voltage to a row line for programming cycles and maintains that same voltage during verify cycles. Instead of changing the row line voltage for the verify cycles, the write circuit selects a bias voltage and current for the column line coupled to the selected cell such that the programming voltage corresponds to the trigger point of a sense amplifier when the selected memory cell has the target threshold voltage. More specifically, when a column line bias circuit supplies a large current, a sense amplifier can sense current through the selected memory cell only if the current through the selected memory cell is correspondingly large. The row line voltage must be higher to achieve the large current through the selected memory cell. With the proper selection of column line bias current, the programming voltage on the row line is also the row line voltage required to trip the sense amplifier when the selected memory cell has the target threshold voltage.
Read and write methods still seek to avoid the noise and charging problems associated with changing the row line voltage, avoid the requirement of a large number of reference cells, and provide an accurate reading and writing of threshold voltages.